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The PMG-M-130 is a  four channel 300 MHz quadrature DDS system incorporating two quadrature analog channels, a clock trigger channel plus an on board fractional Phase Lock Loop with optional VCOs to cover an broad range of frequencies.  The standard frequency range of the two analog channels and the clock trigger channel is 1Hz to 130MHz, the Phase Lock Loop options range is from 100MHz to 300MHz on board  and with daughter-board options in the Gigahertz ranges.  The full length PCI card incorporates eight SMA connectors on the PCI bracket for the primary signal interfaces. Internal Interface connectors allow the connection of optional daughter boards and cabling for off board options. This is an OEM product and the majority of the features here are optional which are tunable to the specific OEM requirements. We have included many of these options available to show the flexibility of this OEM product. For applications that require four identical channels, the PMG-M-130 may be optionally configured as four identical quadrature channels. The flexibility of the PMG-M-130 makes it a valuable addition to your test instrumentation or your test system. The PMG-M-130 was designed and developed by Sal (JT) Tuzzo. For specific details or options not mentioned in this OEM configuration drop us a comment about what your needs are.

PMG-M-130 DDS PCI Card  - Enlarge

PMG-M-130 Application and Development Software Release 1.1

PMG-M-130 Overview

The PMG-M-130 PCI version is a full length PCI card.  The Remote I/O control is an optically isolated optional daughter card that allows the user to control the application remotely through digital logic separated from the CPU and motherboad without CPU intervention.   Understanding that this Remote I/O card maybe used in hostile environments, the Remote I/O Interface card may be purchased separately and replaced if it is damaged by remote equipment failure. As with all of BASIL Networks designs,  a Modular Design Methodology (MDM) philosophy is adhered to that allows easy field servicing of the PMG-M-130 sections that are exposed to the users environment.

The heart of the PMG-M-130 are four 300MHz quadrature DDS controllers.  The main PCI board handles all the digital synthesis, memory control and incorporates a 512 Kbyte high speed SRAM organized as 256K x 16 bit words. This SRAM is use for register tables that govern the behavior of the PMG-M-130. The Internal Behavior Registers (IBR) may be addressed asynchronously in any order allowing behavioral changes that range from a single byte register up to all 255 registers with a single strobe input.

Optional Attachments to the Main PCI board are a variety of analog daughter cards supporting all the analog I/O features. The optional analog daughter card may be replaced with a custom card using our MDM philosophy for the developer who requires a special interface from the PMG-M-130 core engine. The analog card is RF isolated.  The RF outputs are  single ended 50 or 100 ohm drivers that have separate buffers.  There are two high speed digitally controlled gain and offset amplifiers that are optically isolated from the main board as well. The analog daughter board as well as the remote I/O control board may be replaced easily in the event of remote equipment failure. It is the users responsibility to insure the maximum allowable ranges are not exceeded to prevent damage to the PMG-M-130.

The following chapters will discuss the details of the PMG-M-130 software and its control relationship to the hardware. Our website is updated regularly with new application help and FAQ as well as the latest software and manuals.

This TDA presents a tutorial on Modulation Generation Schemes using BASIL Networks PMG-M-130 DDS PCI card.  The PMG-M-130 is capable of generating extremely flexible multi-channel user programmable modulation schemes containing variations of phase, frequency, amplitude and time.  The Schemes are then stored to the on-board RAM and controlled remotely by hardware commands without CPU intervention. The PMG-M incorporates the Analog Devices AD9854 300MHz DDS chip. Your comments are welcome and I may be reached at Sal (JT) for technical discussions. The list below is a few of the programmable modulation schemes the PMG-M-130 is capable of.

The PMG-M-130 Intelligent Integrated Peripherals (I2P) is controlled by programming the Internal / External Behavior Registers (IBR / EBR). There are 16 EBRs and 256 IBR's, 224 of the IBRs are assigned specific tasks within the PMG-M130. The remaining 32 IBRs are user configurable and may be hardware interfaced easily to control external devices. Control of all EBRs and  IBRs are integrated into the application software.  The hardware features for the four channels of the PMG-M-130 are listed below. Each channel has special additive features that will be discussed later in this TDA.


Block Diagram of the Programmable Modulation Generator PMG-M-130

The PMG-M-130 behavior is controlled through two sets of behavioral registers, the Internal Behavioral Registers (IBR) and the External Behavioral Registers (EBR).  The complexity and functionality of the PMG-M-130 is completely under user control, by the setting of the bit assignments within the individual behavioral registers.  All IBRs are synchronized with the Internal System Clock (IntClk) and have a seamless update transfer to the PMG-M’s Active Core (AC).  All changes in behavior setup by these registers are activated by an update pulse that from one of four sources and selectable for each channel. This update pulse will transfer the I/O buffer holding registers to the PMG-M-130  Active Core.

Each channel has four or more IBR that may be user defined for input or output when used with an optional CPLD control interface or the user may create their own. Each channel contains 40 hex ( 64 decimal) IBRs that are used to program each channel.  Any channel above 0x2F that is marked  "Reserved For Future Use" may be user configurable. IBRs ox28 - 0x2F are internally reserved by the PMG-M-130 for future expansion.

The following diagrams below show the fixed IBR assignments for each channel

Channel 1 IBRs'  ANALOG 1 BASE ADDR = 00


Channel 2 IBRs' ANALOG 2 BASE ADDR = 40


Channel 3 IBRs'  CLOCK BASE ADDR = 80

Channel 4 IBRs'  PLL BASE ADDR = C0

The user defined IBRs are externally controlled and may be applied as separate registers using an inexpensive CPLD and can be integrated into any project with ease.  The diagram below shows the assignment layout of these registers. All IBRs are integrated into the software application to simplify the programming and may be updated using a single command strobe for synchronization.

There are 16 USER programmable IBRs (3C - 3F hex offset) for each channel that are identified via an eight bit address and a eight bit data bus using a single strobe pulse integrated into the application software.

External Behavioral Registers (EBR)



The next addition is the reference clock multiplexor.  The Reference Clock Mux Switch allows the user to select the reference or each channel independently from one of four sources. This allows the synchronization of all four channels from a user selected source.

  • Internal 50MHz  -  This is a 50MHz TCXO (+/-25 PPM) reference oscillator with 2ps phase jitter.
  • External Reference  -  A user supplied external reference from 5MHz to 300MHz sinewave or clock squarewave.
  • PLL VCO -  This is the clock output from the Phase Lock Loop Voltage Controlled Oscillator
  • Clock Comparator Channel 3  output  -  This is the comparator output from the clock channel and is user configurable.

The channel 3 clock comparator incorporates a user programmable input to one side of the comparator that may be driven from a user configurable driver and may be synchronized to the clock channel or ground.  This allows a second external clock reference independent of any DDS channel. The comparators incorporated on the PMG-M are fast comparator capable of exceeding 100MHz.


Each channel has the selection of controlling the Frequency Shift Keying and the Phase Shift Keying inputs from one of four sources as shown below. This will allow multiple FSK and PSK when mixing the two output channels through a mixer.  When using the optional Data Transfer attachment the user may synchronize all four channels through a bit stream of various pulse widths and bit rates as well as selecting the high/low frequencies and high/low phase for FSK and PSK applications.  The block diagrams below show the matrix configurations for frequency and phase modulation.



This article is a living document and will constantly be updated as more examples and waveforms are developed and incorporated. If you would like to be on our mailing list as options are presented just drop us a line on our contact form and we will e-mail you when more options are published.

Best Regards,
The BASIL Networks Team

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