SoftwareSRAM SetupSRAM I/ODATA XferDevice SelectDigital OutputSimple  PSKMulti-Freq PSKQAMCommand Line Call

Simple FSK (Frequency Shift Keying)

To start the Multiple Frequency Shift Keying we will show a standard simple FSK operation that does not require the SRAM to program it and use this as the foundation to the multi-frequency FSK. The DDS active core will handle two frequencies, FS-B and FS-A directly into the MODIN pin on the control IO board. The diagram below shows the result from this operation. This is also in the Hardware Manual Chapter 2 Theory of Operation.

When this fundamental mode is selected the output frequency is a function of the values loaded into the Frequency Set A (IBR-04 -09) and B (IBR-0A -0F) registers and the logic level of the MODIN pin on the Remote I/O Control Connector.  A logic “1” selects Frequency Set B and a logic “0” selects  Frequency Set A.  Changes in the frequency are phase-continuous and are internally coincident with the MODIN pin, however, there is a deterministic pipeline delay between the MODIN data signal and the DAC-I andf DAC-Q outputs. These delays are listed in the Specifications section in Appendix D  the Hardware Manual.

The Standard, (No Ramp) FSK, RTTY mode shown in Figure 2.5.0 below shows the relationship between the MODIN pin and the frequency output. FSK is a very reliable mechanism of data communications, however it is inefficient in bandwidth conservation in the RF Spectrum. Ramped FSK (discussed next) is more efficient in conserving the bandwidth.

Figure 2.5.0 Standard FSK Timing Diagram (Unramped)


A simple Multiple Frequency Shift Keying (M-FSK) scheme may be generated with only two control lines, a START Pulse and a SCANDIR (Scan Direction to change frequency) pulse identified as User Supplied in the diagram below..  The selection of the FSK pairs are stored in the on-board SRAM then selected as desired.  The timing diagram below show this along with the serial data bit stream to select the desired FSK results.

Multi-Frequency Shift Keying (M-FSK) Single Blocks Bit stream  timing

Another simple scheme is a series behaviors triggered in a sequential form also requiring only two user supplied pulses, a START and a SCANDIR, similar to before, however the IBR's are stored in the SRAM on board to produce the sequence of frequencies desired. If the FSK mode is used then a series of FSK multiple pairs may be used controlled by the Serial Data Out / MOD-IN pin.

Multi-Frequency Shift Keying (M-FSK)  Multiple Blocks Bit stream  timing

The update of the IBR to the active core is done automatically as shown in the diagram above. however the user may also control the update sequence with the addition of a third user pulse PMG UPDATE as shown in the diagram below.

Multi-Frequency Shift Keying (M-FSK)  Looped Blocks Bit stream  timing

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